DocumentCode :
2905102
Title :
An effective soft module floorplanning algorithm based on sequence pair
Author :
Chi, Jun Cheng ; Chi, Mely Chen
Author_Institution :
Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
fYear :
2002
fDate :
25-28 Sept. 2002
Firstpage :
54
Lastpage :
58
Abstract :
An effective soft module floorplanning algorithm is proposed. It uses simulated annealing framework based on the sequence pair representation. Because a soft module may have many possible shapes, so it will take long time to find a good solution in simulated annealing method. We proposed a method which finds four candidates of module shape to be chosen in a simulated annealing process for each module. These candidates provide a better choice toward local optimal packing. We combine our method with a fast sequence pair evaluation algorithm and keep the same time complexity nlogn of a sequence pair evaluation. During the simulated annealing process, it either chooses to change the shape of one module or to swap the modules in the sequence pair. We have implemented this algorithm. For all MCNC benchmark soft module floorplanning problems, we have obtained more compact floorplan with much less run time comparing to a previous work . For example, for the MCNC benchmark ami49, our algorithm obtained 0.48% of dead space in 142 seconds using a 440 MHz Ultra10 workstation. The previous work to Lagrangian relaxation approach obtained 7.7% of dead space and 2354 seconds using a 600 MHz Pentium III processor.
Keywords :
VLSI; circuit layout CAD; computational complexity; integrated circuit layout; modules; simulated annealing; 142 s; 440 MHz; Lagrangian relaxation approach; MCNC benchmark; Ultra10 workstation; dead space; fast sequence pair evaluation algorithm; local optimal packing; module shape; run time; sequence pair; simulated annealing framework; soft module floorplanning algorithm; time complexity; Circuits; Constraint optimization; Design methodology; Lagrangian functions; Linear programming; Shape; Simulated annealing; Timing; Very large scale integration; Workstations;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
Type :
conf
DOI :
10.1109/ASIC.2002.1158030
Filename :
1158030
Link To Document :
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