Realization of compact low-power ripple-flash A/D converter architectures using conventional digital CMOS technology

In this paper, we present a generalized approach for the construction of ripple-flash ADC architectures that consist of cascade-connected capacitive threshold gates, realized using conventional CMOS technology. The main advantages of the proposed ADC architecture are the very small layout area, simple operation, high input-to-output response speed, and very low power dissipation. A new differential output voltage comparator is presented to ensure high precision and low propagation delay times. Several different ADC implementations are explored, including 4-bit, 5-bit and 6-bit ripple-flash circuit that demonstrate highly accurate DC transfer characteristics with INL errors smaller than 0.1 LSB, and near-ideal SNR levels for sampling frequencies of up to 50 MHz. Test circuits manufactured with 0.8 μm CMOS technology have shown that sampling rates in excess of 50 MHz are possible with this approach, while the silicon area and the power dissipation of the tested ADC circuits remain at least one order of magnitude smaller than those of similar flash ADCs built with the conventional approach.