An 8-bit 200 MS/s CMOS folding/interpolating ADC with a reduced number of preamplifiers using an averaging technique

Author

Heo, Seung-Chan ; Jang, Young-Chan ; Park, Sang-Hune ; Park, Hong-June

Author_Institution

Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea

fYear

2002

fDate

25-28 Sept. 2002

Firstpage

80

Lastpage

83

Abstract

An 8-bit 200 MSample/s CMOS folding/interpolating ADC chip was implemented by using a 0.35-μm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array in comparison with the published folding/interpolating ADC chips. The delay time of digital encoder block was reduced to 1.3 ns from 2.2 ns by using a DCVSPG-style differential logic. The chip area and the measured power consumption were 1.02 mm² and 120 mW respectively at the supply voltage of 3.3 V.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; preamplifiers; 0.35 micron; 1.3 ns; 120 mW; 3.3 V; 8 bit; DCVSPG-style differential logic; averaging technique; delay time; digital encoder block; double-poly CMOS process; folding/interpolating ADC; power consumption; preamplifiers; resistor array; supply voltage; Area measurement; CMOS logic circuits; CMOS process; Delay effects; Energy consumption; Power measurement; Preamplifiers; Resistors; Semiconductor device measurement; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Print_ISBN

0-7803-7494-0

Type

conf

DOI

10.1109/ASIC.2002.1158035

Filename

1158035