Title :
A CMOS Miller hold capacitance sample-and-hold circuit to reduce charge sharing effect and clock feedthrough
Author :
Xu, Weize ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
Abstract :
A technique using Miller capacitance in the sample-and-hold (S/H) circuit is introduced in this paper to reduce the charge sharing effect (CSE) due to the parasitic capacitance and clock feedthrough from a sampling switch. A compact cascode amplifier is used in the Miller feedback circuit and a ten times reduction in CSE and clock feedthrough is achieved. The S/H capacitor is split into two parts, Csh1 and Csh2. One of these S/H capacitors effectively reduces the CSE while the other capacitor reduces clock feedthrough.
Keywords :
CMOS analogue integrated circuits; amplifiers; capacitors; circuit feedback; circuit simulation; integrated circuit design; integrated circuit modelling; integrated circuit noise; sample and hold circuits; switched capacitor networks; CMOS Miller hold capacitance sample-and-hold circuits; CMOS switched capacitor sample-and-hold circuits; CSE; Miller feedback circuits; S/H circuits; charge sharing effect reduction; clock feedthrough reduction; compact cascode amplifiers; parasitic capacitance; sampling switches; split S/H capacitors; CMOS analog integrated circuits; CMOS process; Circuit noise; Clocks; Parasitic capacitance; Sampling methods; Signal processing; Switched capacitor circuits; Switches; Switching circuits;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158037
