Analysis of the single event effects for a 90nm CMOS phase-locked loop

Author

Kauppila, A.V. ; Loveless, T.D. ; Vaughn, G.L. ; Bhuva, B.L. ; Massengill, L.W. ; Holman, W.T.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

201

Lastpage

206

Abstract

A novel approach towards comparing single-event (SE) vulnerability of various components at the function level for a phase-locked loop (PLL) is presented. The technique uses unlock durations and maximum frequency difference after a SE hit to analyze the relative vulnerability of PLL sub-circuits.

Keywords

CMOS integrated circuits; integrated circuit reliability; phase locked loops; CMOS phase locked loop; PLL sub-circuit; single event effect analysis; single event vulnerability; size 90 nm; Charge pumps; Integrated circuit modeling; Phase frequency detector; Phase locked loops; Time frequency analysis; Transistors; Voltage-controlled oscillators; Phase locked loops; single event transients;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on

Conference_Location

Bruges

ISSN

0379-6566

Print_ISBN

978-1-4577-0492-5

Electronic_ISBN

0379-6566

Type

conf

DOI

10.1109/RADECS.2009.5994580

Filename

5994580

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2905280