Fast SER evaluation of embedded RAMs in fault emulation systems

Embedded RAMs have traditionally been a problem for transient fault injection systems based on emulation. Controllability and observability of large RAM blocks available in current digital devices (System-on-Chip, SOCs, and System-on-Programmable-Chip, SOPCs, Multiprocessor-System-On-Chip, MPSOCs) are restricted to data and address buses. It is mandatory, not only to check RAM block reliability itself but also its behaviour within a circuit where transient faults may be propagated from discrete memory elements (flip-flops) towards large memory blocks (RAMs) and vice versa. In this paper, a solution is proposed for checking the robustness of complex digital circuits against single events by means of hardware emulation. A new memory model accelerates emulation campaigns giving enhancements around 90% in fault injection rates.