Clock feedthrough in CMOS analog transmission gate switches

Author

Xu, Weize ; Friedman, Eby G.

Author_Institution

Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA

fYear

2002

fDate

25-28 Sept. 2002

Firstpage

181

Lastpage

185

Abstract

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. Coupling from overlap and MOSFET gate capacitors causes clock feedthrough in TG switches. The slower gate voltage transition provides additional time for the MOSFET to compensate the coupling error on the sample and hold (S/H) capacitor, yielding a smaller clock feedthrough error.

Keywords

CMOS analogue integrated circuits; MOS capacitors; MOSFET; clocks; error analysis; error compensation; field effect transistor switches; integrated circuit modelling; sample and hold circuits; CMOS analog transmission gate switches; MOSFET gate capacitors; capacitor coupling; clock feedthrough; clock feedthrough error; coupling error compensation; current-voltage domain model; gate voltage transition; overlap capacitors; sample and hold capacitor; transmission gate switch model; Capacitors; Clocks; Coupling circuits; Integrated circuit yield; MOS devices; MOSFET circuits; Power semiconductor switches; Semiconductor device modeling; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Print_ISBN

0-7803-7494-0

Type

conf

DOI

10.1109/ASIC.2002.1158052

Filename

1158052