Power reduction via an MTCMOS implementation of MOS current mode logic

Author

Anis, Mohab H. ; Elmasry, Mohamed I.

Author_Institution

VLSI Res. Group, Waterloo Univ., Ont., Canada

fYear

2002

fDate

25-28 Sept. 2002

Firstpage

193

Lastpage

197

Abstract

In this paper, MOS current mode logic (MCML) is implemented in a multi-threshold CMOS technology. The design scheme allows the reduction of the minimum operational supply voltage, as well as the elimination of level shifters used. A high-speed 1:8 2.5 Gbit/s demultiplexer is used as a test vehicle. A 37% power saving is achieved. Furthermore, the impact of using the MTCMOS implementation over circuit parameters such as output impedance, current-matching-ratio, common-mode-rejection-ratio, gain, threshold voltage fluctuations and frequency response is investigated. This work is important for industry since the MTCMOS technique opens a new alley for reducing power in MCML high-speed implementations while attaining the required data rates.

Keywords

CMOS logic circuits; current-mode logic; demultiplexing equipment; high-speed integrated circuits; integrated circuit design; integrated circuit testing; logic design; low-power electronics; 2.5 Gbit/s; MCML high-speed implementation; MOS current mode logic; MTCMOS implementation; circuit gain; circuit parameters; common-mode-rejection-ratio; current-matching-ratio; data rates; design scheme; frequency response; high-speed demultiplexer test vehicle; level shifter elimination; minimum operational supply voltage; multi-threshold CMOS technology; output impedance; power reduction; power saving; threshold voltage fluctuations; CMOS logic circuits; CMOS technology; Circuit testing; Energy consumption; Frequency; Impedance; Power dissipation; Threshold voltage; Vehicles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Print_ISBN

0-7803-7494-0

Type

conf

DOI

10.1109/ASIC.2002.1158055

Filename

1158055