Title :
A low-voltage low-noise CMOS digital family
Author :
Secareanu, Radu M. ; Hartman, Davis
Author_Institution :
Digital DNA(TM) Labs., Motorola Inc., Tempe, AZ, USA
Abstract :
A CMOS logic family is proposed. The primary characteristic of this logic family is the low voltage operation (VDD between one and two transistor threshold voltages (VTs), with a typical VDD = 1.5 VT). While operating at this reduced power supply, low noise and high performance (such as high speed, low power, and high noise margins) are achieved.
Keywords :
CMOS logic circuits; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; low-power electronics; 0.4 V; 0.7 V; high noise margin CMOS; high performance CMOS logic; low-voltage low-noise CMOS digital family; power supply reduction; transistor threshold voltages; CMOS logic circuits; CMOS technology; Circuit noise; Logic devices; Low voltage; Nanoscale devices; Noise reduction; Power supplies; Semiconductor device noise; Threshold voltage;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158056
