Area-efficient VLSI implementation of FIR digital filters using shifted partial products

The authors describe a novel method of computing scalar-vector products based on shifted partial products of the vector elements. The method achieves a several-fold reduction in the computation required to implement a scalar-vector product. Of interest is the application of this idea to the highly parallel, area-efficient VLSI implementation of a finite impulse response digital filter in the transpose form. The reduction in computation translates into an overall decrease in chip area required for a VLSI layout of the filter. As an example in a representative VLSI technology, a pipelined design yields a 30% decrease in chip area per tap and a 20% decrease in overall chip area compared to a modified Booth´s multiplier implementation