• DocumentCode
    2905647
  • Title

    A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process

  • Author

    Chou, Wen-Shen ; Yang, Shu-Chieh ; Hsueh, Fu-Lung ; Huang, Heng-Chang ; Hsiao, Chih-Ji

  • Author_Institution
    TSMC Design & Technol. Platform, Hsinchu
  • fYear
    2007
  • fDate
    27-30 May 2007
  • Firstpage
    3594
  • Lastpage
    3597
  • Abstract
    An area-optimized 10-bit current steering, triple-channel video DAC IP designed in 65nm, 1.2V/2.5V CMOS process is described. Each channel of DAC can drive an output load of 37.5 ohms to provide a maximum output voltage 1.278V. The measured DNL and INL at 250MHz are less than 1 LSB and 2 LSB, respectively. This DAC IP is optimized with small area for low cost embedded SOC applications. It has area of 0.22mm2, which is the smallest IP in market.
  • Keywords
    CMOS integrated circuits; digital-analogue conversion; 1.2 V; 1.278 V; 10 bit; 2.5 V; 250 MHz; 37.5 ohm; 65 nm; CMOS process; differential nonlinearity performance; digital-to-analog converter; integral nonlinearity performance; Availability; CMOS process; CMOS technology; Circuits; Cost function; Decoding; Latches; Photonic band gap; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
  • Conference_Location
    New Orleans, LA
  • Print_ISBN
    1-4244-0920-9
  • Electronic_ISBN
    1-4244-0921-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2007.378530
  • Filename
    4253458
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2905647