DocumentCode
2905673
Title
Implementation of pin point landing vision components in an FPGA system
Author
Morfopolous, Arin ; Metz, Brandon ; Villalpando, Carlos ; Matthies, Larry ; Serrano, Navid
Author_Institution
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fYear
2011
fDate
5-12 March 2011
Firstpage
1
Lastpage
9
Abstract
Pin-point landing is required to enable missions to land close, typically within 10 meters, to scientifically important targets in generally hazardous terrain. In Pin Point Landing both high accuracy and high speed estimation of position and orientation is needed to provide input to the control system to safely choose and navigate to a safe landing site. A proposed algorithm called VISion aided Inertial NAVigation (VISINAV) has shown that the accuracy requirements can be met. [2][3] VISINAV was shown in software only, and was expected to use FPGA enhancements in the future to improve the computational speed needed for pin point landing during Entry Descent and Landing (EDL). Homography, feature detection and spatial correlation are computationally intensive parts of VISINAV. Homography aligns the map image with the descent image so that small correlation windows can be used, and feature detection provides regions that spatial correlation can track from frame to frame in order to estimate vehicle motion. On MER the image Homography, Feature Detection and Correlation would take approximately 650ms tracking 75 features between frames. We implemented Homography, Feature detection and Correlation on a Virtex 4 LX160 FPGA to run in under 25ms while tracking 500 features to improve algorithm reliability and throughput.
Keywords
aircraft landing guidance; feature extraction; field programmable gate arrays; FPGA system; control system; descent image; entry descent; feature detection; hazardous terrain; homography; map image; pin point landing vision component; spatial correlation; vision aided inertial navigation; Correlation; Correlators; Engines; Feature extraction; Field programmable gate arrays; Pixel; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Aerospace Conference, 2011 IEEE
Conference_Location
Big Sky, MT
ISSN
1095-323X
Print_ISBN
978-1-4244-7350-2
Type
conf
DOI
10.1109/AERO.2011.5747245
Filename
5747245
Link To Document