A massively parallel RNS architecture

Author

Elleithy, Khaled M. ; Bayoumi, Magdy A.

Author_Institution

Dept. of Comput. Eng., King Fahd Univ. of Pet. & Min., Dhahran, Saudi Arabia

fYear

1991

fDate

4-6 Nov 1991

Firstpage

408

Abstract

Parallelism on the algorithmic, architectural, and arithmetic levels is exploited in the design of a residue number system (RNS) based architecture. The architecture is based on modulo processors. Each modulo processor is implemented by a two-dimensional systolic array composed of very simple cells. The decoding state is implemented using a two-dimensional array. The decoding bottleneck is eliminated. The whole architecture is pipelined, which leads to a high throughput rate. High speed algorithms for modulo addition, modulo multiplication, and RNS decoding are presented

Keywords

digital arithmetic; pipeline processing; systolic arrays; RNS decoding; arithmetic parallelism; decoding state; design; high speed algorithms; massively parallel RNS architecture; modulo addition; modulo multiplication; modulo processors; pipelined architecture; two-dimensional systolic array; Computer architecture; Concurrent computing; Decoding; Design engineering; Digital arithmetic; Minerals; Parallel processing; Petroleum; Systolic arrays; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-2470-1

Type

conf

DOI

10.1109/ACSSC.1991.186482

Filename

186482