Title :
Next generation CoreConnect™ processor local bus architecture
Author :
Hofmann, Rick ; Drerup, B.
Author_Institution :
IBM Microelectron., Boca Raton, FL, USA
Abstract :
The CoreConnect™ next generation Processor Local Bus is a new, advanced technology bus architecture from IBM. This new bus architecture is substantially improved over previous generations, continuing its performance and feature leadership in high performance, open SOC buses. CoreConnect™ is targeted for high performance embedded applications in wired and wireless communications, networking, storage, and pervasive applications. This architecture provides SOC designers with a low power, high performance on-chip bus with server-class capabilities for single and multiple processors.
Keywords :
integrated circuit design; integrated circuit interconnections; integrated memory circuits; low-power electronics; system buses; system-on-chip; CoreConnect processor local bus architecture; SOC design; embedded applications; low power on-chip bus; multiple processors; multiprocessing; networking applications; open SOC buses; single processors; storage applications; systems-on-a-chip; wired communications; wireless communications; Bandwidth; Clocks; Control systems; Data buses; Frequency; Protocols; Registers; System-on-a-chip; Timing; Wireless communication;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158060
