Title :
Complementary substrate-triggered SCR devices for on-chip ESD protection circuits
Author :
Ker, Ming-Dou ; Hsu, Kuo-Chun
Author_Institution :
Inst. of Electron., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
The turn-on mechanism of the SCR device is essentially a current triggering event. When a current is applied to the base or substrate of a SCR device, it can be quickly triggered into its latching state. In this paper, the complementary substrate-triggered SCR devices, which are a combination of the substrate-triggering technique and SCR devices, are first reported in the literature for use in on-chip ESD protection circuits. The complementary style of the substrate-triggered SCR devices is designed to discharge both positive and negative ESD stresses on the pad. The total holding voltage of the substrate-triggered SCR device can be increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices for the I/O pad and power pad have been successfully verified in a 0.25-μm STI CMOS process with the HBM (MM) ESD level of >8 kV (650 V) in a small layout area.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit measurement; integrated circuit reliability; isolation technology; protection; thyristors; 0.25 micron; 650 V; 8 kV; HBM ESD level; I/O pad; MM ESD level; SCR triggering; SCR turn-on mechanism; STI CMOS process; complementary substrate-triggered SCR devices; current triggering event; latching state; layout area; negative ESD stress discharge; on-chip ESD protection circuits; positive ESD stress discharge; power pad; stacked diode string; total holding voltage; transient-induced latchup; CMOS process; CMOS technology; Circuits; Diodes; Electrostatic discharge; Power supplies; Protection; System-on-a-chip; Thyristors; Voltage;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158061