Algorithm and architectures for radix-4 division with over-redundant digit set and simple digit selection hardware

The authors analyze a SRT radix 4-division algorithm which has a trivial selection function. The algorithm uses an over-redundant digit set together with the same prescaling considered by M.D. Ercegovac and T. Lang, (1990) where, however, it is shown that the digit selection requires the knowledge of six assimilated bits of the partial remainder in order to work correctly. Architectures for implementing the proposed algorithm are also presented, which can be considered as alternatives to the existing architectures for radix-4 division. An architectural solution to the problem of on-the-fly translating of the quotient from over-redundant to non-redundant form is provided