High-radix systolic modular multiplication on reconfigurable hardware

The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to precompute or store any multiples of the operands is avoided. This also allows very high radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512 bit and 1024 bit FPGA implementations using radices of 2⁸ and 2¹⁶ are presented. The subsequent throughput rates are the fastest reported to date