Title :
High-radix systolic modular multiplication on reconfigurable hardware
Author :
McIvor, Ciaran ; McLoone, Máire ; McCanny, John V.
Author_Institution :
Inst. of Electron., Commun. & Inf. Technol., Queen´´s Univ. Belfast
Abstract :
The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to precompute or store any multiples of the operands is avoided. This also allows very high radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512 bit and 1024 bit FPGA implementations using radices of 28 and 216 are presented. The subsequent throughput rates are the fastest reported to date
Keywords :
digital arithmetic; field programmable gate arrays; logic design; multiplying circuits; reconfigurable architectures; systolic arrays; FPGA implementation; Montgomery modular multiplication architecture; Montgomery multiplier design; adder; field programmable gate array; high radix systolic array; processing element; reconfigurable hardware; Cryptographic protocols; Cryptography; Electronic mail; Field programmable gate arrays; Hardware; Information technology; Protection; Software algorithms; Throughput; Virtual private networks;
Conference_Titel :
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Conference_Location :
Singapore
Print_ISBN :
0-7803-9407-0
DOI :
10.1109/FPT.2005.1568518