The Technique Research on FBP

Summary form only given. As the development of semiconductor manufacturing technology, it will force the packaging technology to develop correspondingly to meet the requests of different IC functions. FBP (Flat Bump Package), designed by JCET, is the package to meet those requests with its high thermal/electrical performance, low interference, strong joint strength and excellent reliability. Furthermore FBP is suitable for many dices such as diode, dynatron, field effect transistors, power IC, RF IC, logic IC, memory IC, driver IC, power management IC and so on. Compared with other leadless packages like QFN/DFN/BCC. FBP has mam improvements like option for epoxy /soft solder/eutectic, no resin bleeding issue, strip testing capability, excellent bond-ability in SMT, die pad mounting to motherboard, low package thickness profile (down to 0.35mm), high I/O capacity (400, 1-3 rows of leads), MCM and embedded passives capability, flexible configuration options and excellent electrical/thermal performance. FBP is JECT patent technology. There are more than 30 patents on FBP domestically and internationally, and more than 10 patents have been authorized by State Intellectual Property Office of P.R.C. In this paper, the special structure and excellent performance of FBP are introduced, described and illustrated graphically.