A VLSI array architecture for the on-line training of recurrent neural networks

Author

Kechriotis, George ; Manolakos, Elias S.

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

1991

fDate

4-6 Nov 1991

Firstpage

506

Abstract

The authors show how to derive systematically a VLSI systolic array for the real time recurrent learning (RTRL) algorithm of D. Zipser and R.J. Williams (1989). The main goal is to match the RTRL algorithm to the ring architecture proposed by J.N. Hwang et al. (1990) that was shown to be generally applicable to many neural network models. Although this task was a straightforward extension for the retrieving phase, skillful reformulation of the learning phase was necessary. The control complexity and memory requirements of the processing elements remain reasonably low

Keywords

VLSI; learning systems; neural nets; systolic arrays; RTRL algorithm; VLSI array architecture; VLSI systolic array; control complexity; memory requirements; on-line training; processing elements; real time recurrent learning; recurrent neural networks; Application software; Computer architecture; Encoding; Limit-cycles; Neural networks; Phased arrays; Recurrent neural networks; Speech processing; State-space methods; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on

Conference_Location

Pacific Grove, CA

ISSN

1058-6393

Print_ISBN

0-8186-2470-1

Type

conf

DOI

10.1109/ACSSC.1991.186501

Filename

186501