Title :
Chip Package Interaction in Ultra Low-k/Copper Interconnect Technology
Author :
Liu, X.H. ; Shaw, T.M. ; Liniger, E.G. ; Lane, M.W. ; Bonilla, G. ; Doyle, J.P. ; Herbst, B.W. ; Questad, D.L.
Author_Institution :
IBM, Yorktown Heights
Abstract :
In this paper a methodology based on fracture mechanics has been used to investigate the chip package interaction of ultra low-k/copper interconnect. When a wafer is diced into chips, defects can be generated at the edge of the chips. Under the thermal stress from the package the defects can propagate into the dielectric and cause the chip failure.
Keywords :
chip scale packaging; fracture mechanics; integrated circuit interconnections; integrated circuit modelling; integrated circuit reliability; thermal stresses; Cu; chip failure; chip scale packaging; fracture mechanics; thermal stress; ultra low-k/copper interconnect technology; Copper; Delamination; Dielectric measurements; Finite element methods; Mechanical factors; Packaging; Semiconductor device measurement; Testing; Thermal force; Thermal stresses;
Conference_Titel :
Electronic Packaging Technology, 2007. ICEPT 2007. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1392-8
Electronic_ISBN :
978-1-4244-1392-8
DOI :
10.1109/ICEPT.2007.4441569
