Title :
Long-term power minimization of dual-VT CMOS circuits
Author :
Kim, Suhwan ; Shin, Youngsoo ; Kosonocky, Stephen ; Hwang, Wei
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
In this paper, we define long-term power dissipation in which the effect of the system-level power management on the total power dissipation of a given circuit is considered. Then, we present a novel design methodology to minimize the long-term power dissipation of a circuit used along with dual-threshold voltage selection and voltage scaling. In simulation on 16-bit carry lookahead adders (CLAs), the proposed approach can reduce up to 80% and 25% of the total power dissipation along with clock- and power-gating, respectively.
Keywords :
CMOS logic circuits; adders; carry logic; circuit optimisation; circuit simulation; integrated circuit design; logic design; logic simulation; minimisation; 16 bit; CLA; carry lookahead adders; clock-gating; design methodology; dual-VT CMOS circuits; dual-threshold voltage selection; long-term power minimization; power dissipation; power-gating; simulation; system-level power management; voltage; Circuits; Clocks; Energy consumption; Energy management; Equations; MOSFETs; Minimization; Power dissipation; Sleep; Timing;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158079
