A low-power UHF RF frontend for a low-IF receiver

Author

Zencir, Ertan ; Dogan, Numan S. ; Arvas, Ercument

Author_Institution

Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

fYear

2002

fDate

25-28 Sept. 2002

Firstpage

331

Lastpage

335

Abstract

A low-power 435 MHz RF front end was implemented in a 0.5 μm CMOS process that is intended for use in a low-power low-IF receiver under development for deep space communication. The RF front end includes a differential low-noise amplifier (LNA) with on-chip spiral inductors and a doubly balanced mixer which downconverts the LNA output to 2 MHz IF. The front end has a simulated noise figure of 3.8 dB, input 1-dB compression point of -42 dBm, input third-order intercept point of -34 dBm, and conversion gain of 54 dB. Total power dissipation is 15 mW. The area occupied by the chip is 1.3 mm × 1.9 mm.

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; UHF mixers; inductors; integrated circuit design; integrated circuit measurement; integrated circuit modelling; low-power electronics; radio receivers; space vehicle electronics; 0.5 micron; 1.3 mm; 1.9 mm; 15 mW; 2 MHz; 3.8 dB; 435 MHz; 54 dB; CMOS low-power UHF RF front ends; LNA noise figure; LNA output downconversion; chip area; conversion gain; differential low-noise amplifiers; doubly balanced mixers; input compression point; input third-order intercept point; low-IF deep space communication receivers; on-chip spiral inductors; power dissipation; Circuits; Inductance; Inductors; Low-noise amplifiers; Mixers; Noise figure; Power dissipation; Q factor; Radio frequency; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 2002. 15th Annual IEEE International

Print_ISBN

0-7803-7494-0

Type

conf

DOI

10.1109/ASIC.2002.1158080

Filename

1158080