A Dual-Threshold FPGA Routing Design for Subthreshold Leakage Reduction

Field-programmable gate arrays are attractive candidates for wireless applications due to their reconfiguration capability and high performance development. However, sub-threshold leakage power in modern FPGAs has become a critical obstacle for these devices in entering to this application domain. Subthreshold leakage current of programmable interconnections is responsible for most of the static power dissipation. This work proposes and evaluates ten routing designs based on the dual-threshold technique to reduce leakage power. Alternating between buffers and pass transistors, we analyze the percentage constitution of low-V_th and high-V_th transistors as a function of the leakage reduction and delay increment tradeoff. By routing a suite of MCNC benchmark circuits, we show that an average savings of about 28.83% (as high as 48.46%) in total interconnect leakage can be obtained with 8.73% worst case average delay penalty.