Delay Variability Due to Supply Variations in Transmission-Gate Full Adders

In this paper, the delay variability due to supply variations is investigated for the transmission-gate (TG) full adder topology, which is well known for its very low power consumption. The delay sensitivity with respect to supply variations is first analytically modeled. The resulting model is very simple, independent of the adopted technology and useful for better understanding the delay variations due to the supply voltage fluctuations. The delay sensitivity with respect to supply variations is also compared with that of traditional CMOS full adders, that are frequently adopted as a reference logic style. The results are validated by means of Spectre simulations with a 90-nm and a 0.18-mum technology.