Title :
Scaled accumulation FETs for ultra-low power logic
Author :
Murali, Raghunath ; Austin, Blanca L. ; Wang, Lihui ; Meindl, James D.
Author_Institution :
Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
Ultra-low power systems require very low standby power and operate at moderate speeds. Traditionally, the normal surface channel inversion (SCI) FET would be considered better for such applications when compared to the buried channel (BC) FET, since the BC FET has always shown more short channel effects in past research. However, past comparisons between the two FETs have been done with the highest frequency in mind and the same conclusion need not hold true for moderate speed, ultra-low power applications. Due to a better subthreshold slope and negligible band to band tunneling leakage at the drain-halo and drain-channel region, the BC FET is better suited for such applications.
Keywords :
buried layers; field effect logic circuits; field effect transistors; integrated circuit modelling; logic design; low-power electronics; semiconductor device models; BC FET; SCI FET; band to band tunneling leakage; buried channel FET; drain-channel region; drain-halo region; moderate speed applications; operating speed; scaled accumulation FET; short channel effects; standby power; subthreshold slope; surface channel inversion FET; ultra-low power logic; Analytical models; Application software; Doping; FETs; Leakage current; Logic; Medical simulation; Numerical models; Numerical simulation; Semiconductor process modeling;
Conference_Titel :
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Print_ISBN :
0-7803-7494-0
DOI :
10.1109/ASIC.2002.1158087