DocumentCode
2906618
Title
Heuristics for context-caches in 2-level reconfigurable architectures
Author
Lange, Sebastian ; Middendorf, Martin
Author_Institution
Parallel Comput. & Complex Syst. Group, Leipzig Univ., Germany
fYear
2005
fDate
11-14 Dec. 2005
Firstpage
293
Lastpage
294
Abstract
Heuristics for the use of a context cache in multi-context 2-level reconfigurable architectures are proposed. These architectures can be dynamically reconfigured on two different levels. The lower level allows to perform ordinary reconfiguration operations on the reconfigurable resources. On the upper reconfiguration level the reconfiguration capabilities of the reconfigurable resources that are available for the lower level reconfiguration can be reconfigured. We consider 2-level reconfigurable architectures with a cache for contexts that correspond to the upper reconfiguration level. Different heuristics to select the contexts that are stored in the cache are proposed in order to reduce the total reconfiguration costs.
Keywords
cache storage; logic design; reconfigurable architectures; context cache; multicontext 2 level reconfigurable architectures; reconfiguration level; Computer architecture; Costs; Field programmable gate arrays; Parallel processing; Reconfigurable architectures; Switches; Testing; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Technology, 2005. Proceedings. 2005 IEEE International Conference on
Print_ISBN
0-7803-9407-0
Type
conf
DOI
10.1109/FPT.2005.1568567
Filename
1568567
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