Low Power SoC Memory BIST

Author

Wu, Yuejian ; Ivanov, Andre

Author_Institution

Nortel, Ottawa, Ont.

fYear

2006

fDate

Oct. 2006

Firstpage

197

Lastpage

205

Abstract

With the ever increasing number of memories embedded in a system-on-chip (SoC), power dissipation due to test has become a serious concern. This paper studies power dissipation in SRAMs and proposes a novel low power memory BIST. Its effectiveness is evaluated on memories in 130 and 90 nm technologies. As demonstrated, up to 30% power reduction can be achieved with virtually zero hardware overhead

Keywords

SRAM chips; built-in self test; embedded systems; integrated circuit testing; low-power electronics; nanobiotechnology; system-on-chip; 130 nm; 90 nm; BIST; SRAM; SoC memory; embedded system; integrated circuit testing; low power dissipation; low power memory; nanotechnology; system-on-chip; virtual zero hardware overhead; Automatic testing; Built-in self-test; Capacitance; Decoding; Logic testing; Power dissipation; Proposals; Silicon; System-on-a-chip; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on

Conference_Location

Arlington, VA

ISSN

1550-5774

Print_ISBN

0-7695-2706-X

Type

conf

DOI

10.1109/DFT.2006.39

Filename

4030930

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2906675