Title :
A Novel Low Power BPSK Demodulator
Author :
Luo, Zhenying ; Sonkusale, Sameer
Author_Institution :
Dept. of Electr. & Comput. Eng., Tufts Univ., Medford, MA
Abstract :
A novel low power binary phase shift keying (BPSK) demodulator architecture is presented. The design employs a phase frequency detector (PFD) based phase locked loop (PLL), which allows for low power consumption and a higher tracking and locking range compared to prior art. Using the proposed architecture, a 13.5 MHz BPSK demodulator has been designed and fabricated in a 0.5mum CMOS technology. Simulation and chip measurement result show that this BPSK demodulator provides low power operation and robust performance.
Keywords :
CMOS integrated circuits; demodulators; detector circuits; low-power electronics; phase locked loops; phase shift keying; 0.5 micron; 13.5 MHz; BPSK demodulator; CMOS technology; PLL; binary phase shift keying demodulator architecture; phase frequency detector; phase locked loop; Art; Binary phase shift keying; CMOS technology; Demodulation; Energy consumption; Phase frequency detector; Phase locked loops; Power measurement; Semiconductor device measurement; Tracking loops;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.377880
