DocumentCode
2906891
Title
Online hardening of programs against SEUs and SETs
Author
Lisbôa, C. A L ; Carro, L. ; Reorda, M. Sonza ; Violante, M.
Author_Institution
Inst. de Informdtica, Univ. Fed. do Rio Grande do Sul, Porto Alegre
fYear
2006
fDate
Oct. 2006
Firstpage
280
Lastpage
290
Abstract
Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs´ dependability. However, SIHFT increases the time for running the hardened application, and the memory occupation. In this paper we propose a method that eliminates the memory overhead, using a new approach to instruction hardening and control flow checking during the execution of the application, without the need for introducing any change in its source code. The proposed method is also non-intrusive, since it does not require any modification in the main processor´s architecture. The method is suitable for hardening SoCs against transient faults and also for detecting permanent faults
Keywords
embedded systems; fault tolerance; instruction sets; microprocessor chips; system-on-chip; SET; SEU; control flow checking; hardware hardening; instruction hardening; memory overhead; online hardening; permanent faults; processor cores; software implemented hardware fault tolerance; systems-on-a-chip; transient faults; Application software; Computer aided instruction; Costs; Fault detection; Fault tolerance; Hardware; Mission critical systems; Safety; Single event transient; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location
Arlington, VA
ISSN
1550-5774
Print_ISBN
0-7695-2706-X
Type
conf
DOI
10.1109/DFT.2006.49
Filename
4030939
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