DocumentCode
2907069
Title
Polynomial formal verification of of multipliers
Author
Keim, Martin ; Martin, Michael ; Becker, Bernd ; Drechsler, Rolf ; Molitor, Paul
Author_Institution
Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
fYear
1997
fDate
27 Apr-1 May 1997
Firstpage
150
Lastpage
155
Abstract
Until recently verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time when applied to the class of Wallace-tree like multipliers
Keywords
Boolean functions; circuit analysis computing; combinational circuits; data structures; formal verification; logic CAD; polynomials; trees (mathematics); 256 bit; Boolean variables; Wallace-tree like multipliers; arithmetic functions; data structure; input word sizes; logic verification; multiplicative binary moment diagram; polynomial formal verification; Arithmetic; Boolean functions; Circuit testing; Computer science; Costs; Data structures; Formal verification; Logic; Polynomials; Process design;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location
Monterey, CA
ISSN
1093-0167
Print_ISBN
0-8186-7810-0
Type
conf
DOI
10.1109/VTEST.1997.599468
Filename
599468
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