Title :
Robust platform design in advanced VLSI technologies
Author :
Leavins, David J. ; Kim, Kee Sup ; Mitra, Subhasish ; Rodriguez, Eddie J.
Author_Institution :
Intel Corp., Sacramento, CA, USA
Abstract :
The traditional paradigm of conservative design and thorough production testing is not sufficient for designing robust platforms in advanced VLSI technologies. Fundamentally new techniques are required for incorporating new design features for thorough testing, yield improvement, error detection and correction, self-recovery and repair. This represents a new direction in the ´design for´ techniques in the areas of test, reliability and manufacturability. This paper presents an overview of two such techniques: a test compression technique for exponential reduction in test time and test data volume, and a built-in soft error resilience technique that enables more than 20-fold reduction in the susceptibility of system latches and flip-flops to radiation-induced transient errors.
Keywords :
VLSI; built-in self test; design for testability; fault tolerance; integrated circuit design; integrated circuit testing; VLSI technologies; error correction; error detection; flip-flops; production testing; radiation-induced transient error; self-recovery; soft error resilience; system latches; test compression; test data volume; test time reduction; yield improvement; Automatic testing; Circuit testing; Costs; Design for testability; Flip-flops; Logic testing; Production; Robustness; System testing; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568599
