DocumentCode :
2907164
Title :
Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method
Author :
Chen, Ying-Yen ; Liou, Jing-Jia
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
fYear :
2006
fDate :
Oct. 2006
Firstpage :
428
Lastpage :
438
Abstract :
In this paper, we apply a technique to improve diagnosis resolution for delay faults. The method analyze the structure of test paths to find the bottleneck of the diagnosis process. Then we use the information to search for additional paths (by extending from the current paths) in order to effectively cut down the number of faulty candidates. The experimental result shows that the proposed technique can reduce the efforts of diagnosis by a meaningful amount. In ISCAS´89 benchmarks, the method can improve the average ranks of injected defects in the suspect list from 9.14 to 5.97 as injected delay size is 1% of longest paths
Keywords :
fault diagnosis; integrated circuit testing; delay faults; diagnosis resolution; path extension method; Circuit faults; Circuit testing; Delay; Fault diagnosis; Fault tolerant systems; Inspection; Logic; Process design; Timing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
Conference_Location :
Arlington, VA
ISSN :
1550-5774
Print_ISBN :
0-7695-2706-X
Type :
conf
DOI :
10.1109/DFT.2006.27
Filename :
4030955
Link To Document :
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