Scalable bus interface for HSDPA co-processor extension

This paper presents a scalable bus developed for HSDPA co-processor extension of W-CDMA digital baseband processors. The use of two separate buses (one for control messages and one for transmission and reception data) in a multimaster bus design helps keep down bus occupancy and CPU loads. The design offers high scalability for future extension and single-chip implementation, as well as a 66% reduction in bus occupancy over that of conventional memory bus connections. Further, with the addition of a MAC accelerator, the design achieves a 45% CPU-load reduction.