• DocumentCode
    2907254
  • Title

    Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations

  • Author

    Zhang, Fengming ; Necoechea, Warren ; Reiter, Peter ; Kim, Yong-Bin ; Lombardi, Fabrizio

  • Author_Institution
    LTX Corp.
  • fYear
    2006
  • fDate
    4-6 Oct. 2006
  • Firstpage
    486
  • Lastpage
    494
  • Abstract
    This paper presents two load board designs for hierarchical calibration of largely populated ATE. Compound dot technique and phase detector are used on both boards to provide automatic and low cost calibration of ATE with or without a single reference clock. Two different relay tree structures are implemented on the two boards with advanced board design techniques for group offset calibration. Various error sources have been identified and analyzed on both boards based on SPICE simulations and real measurements. TDR measurement compares the two approaches and shows that the two load boards give a maximum of 37ps group timing skew and can be calibrated out by the calibration software
  • Keywords
    SPICE; automatic test equipment; calibration; circuit simulation; integrated circuit measurement; integrated circuit testing; phase detectors; SPICE simulations; TDR measurement; compound dot technique; group offset calibration; hierarchical ATE calibrations; load board designs; phase detector; relay tree structures; Analytical models; Calibration; Clocks; Costs; Detectors; Phase detection; Relays; SPICE; Software measurement; Tree data structures;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
  • Conference_Location
    Arlington, VA
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-2706-X
  • Type

    conf

  • DOI
    10.1109/DFT.2006.38
  • Filename
    4030961