A low-area decimation filter for ultra-high speed 1-bit ΣΔ A/D converters

Author

Muhammad, K. ; Elahi, I. ; Jung, T.

Author_Institution

Texas Instruments Inc., Dallas, TX, USA

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

77

Lastpage

80

Abstract

We present a low-area and low-power implementation of the first antialiasing and decimation filter following an ultra-high speed 1-bit ΣΔ A/D converter operating between 430-600Msps in a wireless transceiver. This filter is implemented as a sinc⁴ polyphase structure that decimates by 16. Reduction in area is achieved by interleaving I and Q data and by implementing each phase of the filter as a hard-wired lookup table. The filter provides more than 150 dB of rejection in 400 kHz band and more than 87 dB of rejection in 4 MHz band making it suitable for multistandard wireless applications. It is implemented in 90-nm digital CMOS process and the combined area for both I and Q channels is less than 3800 gates.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; digital filters; low-power electronics; sigma-delta modulation; ΣΔ A/D converters; 1 bit; 4 MHz; 400 kHz; 90 nm; I channel; Q channel; antialiasing filter; digital CMOS process; lookup table; low-area decimation filter; wireless transceiver; Clocks; Dynamic range; Filtering; Finite impulse response filter; Frequency; GSM; Interleaved codes; Power dissipation; Table lookup; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568612

Filename

1568612