• DocumentCode
    2907344
  • Title

    A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network

  • Author

    Horita, Tadayoshi ; Murata, Takurou ; Takanami, Itsuo

  • Author_Institution
    Dept. of Inf. & Comput. Sci., Polytech. Univ., Brooklyn, NY
  • fYear
    2006
  • fDate
    4-6 Oct. 2006
  • Firstpage
    554
  • Lastpage
    562
  • Abstract
    This paper introduces an implementation method of multiple weight as well as neuron fault-tolerant multilayer neural networks. Their fault-tolerance is derived from our extended back propagation learning algorithm called the deep learning method. The method can realize a desired weight as well as neuron fault-tolerance in multilayer neural networks where weight values are floating-point and the sigmoid function is used to calculate neuron output values. In this paper, fault-tolerant multilayer neural networks are implemented as digital circuits where weight values are quantized and the step function is used to calculate neuron output values using the deep learning method, the VHDL notation, and the logic design software QuartusII of Altera Inc. The efficiency of our method is shown in terms of fabrication-time cost, hardware size, neural computing time, generalization property, and so on
  • Keywords
    backpropagation; fault tolerance; field programmable gate arrays; floating point arithmetic; hardware description languages; neural nets; Altera Inc.; FPGA; QuartusII; VHDL notation; back propagation learning algorithm; deep learning; digital circuits; floating-point; logic design software; multilayer neural network; multiple-weight neural network; neuron fault; neuron-fault tolerant neural network; sigmoid function; weight fault; Circuit faults; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Hardware; Learning systems; Logic design; Multi-layer neural network; Neural networks; Neurons; FPGA; VHDL; fault tolerance; multilayer neural network; neuron fault; weight fault;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Defect and Fault Tolerance in VLSI Systems, 2006. DFT '06. 21st IEEE International Symposium on
  • Conference_Location
    Arlington, VA
  • ISSN
    1550-5774
  • Print_ISBN
    0-7695-2706-X
  • Type

    conf

  • DOI
    10.1109/DFT.2006.8
  • Filename
    4030968