Algorithmic design methodologies and design porting of wireline transceiver IC building blocks between technology nodes

Author

Voinigescu, S.P. ; Dickson, T.O. ; Chalvatzis, T. ; Hazneci, A. ; Laskin, E. ; Beerkens, R. ; Khalid, I. ; Rogers, Edward S.

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

2005

fDate

18-21 Sept. 2005

Firstpage

111

Lastpage

118

Abstract

This paper presents an analysis of sub-2.5-V topologies and design methodologies for SiGe BiCMOS and sub-90nm CMOS building blocks to be used in the next generation of 40-100 Gb/s wireline transceivers. Examples of optimal designs for 40-80Gb/s broadband low-noise input comparators, low-voltage high-speed MOS- and BiCMOS CML logic gates, 30-100 GHz low-noise oscillators, and 40/80 GHz output drivers with wave shape control are provided.

Keywords

BiCMOS logic circuits; CMOS integrated circuits; Ge-Si alloys; MOS logic circuits; comparators (circuits); current-mode logic; driver circuits; integrated circuit design; oscillators; transceivers; 2.5 V; 30 to 100 GHz; 40 to 100 Gbit/s; 90 nm; BiCMOS CML logic gates; BiCMOS building block; CMOS building block; MOS logic gates; SiGe; algorithmic design methodologies; broadband low-noise input comparators; low-noise oscillators; output drivers; wave shape control; wireline transceivers; Algorithm design and analysis; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Design methodology; Germanium silicon alloys; Logic gates; Silicon germanium; Topology; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568621

Filename

1568621