Notice of Violation of IEEE Publication PrinciplesA 10.7GHz SiGe BICMOS limiting amplifier using multiple offset cancellation loops

Notice of Violation of IEEE Publication Principles

"A 10.7GHz SiGe BICMOS limiting amplifier using multiple offset cancellation loops"
by Maxim, A.
in the Proceedings of the IEEE 2005 Custom Integrated Circuits Conference,
18-21 Sept. 2005 Page(s):127 - 130

After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.

A 10.7GHz limiting amplifier was realized in a 0.2μm 60GHz f/sub T/ SiGe BICMOS process by using a signal path implemented with a cascade of emitter followers and differential stages using dual capacitive peaking networks. The output offset voltage was reduced to fractions of mV by using individual active offset cancellation loops for each gain stage. Their compensation capacitors were integrated on-chip with the help of a Miller multiplication architecture. ICs specifications include: >60dB signal path gain, <0.2mV output offset voltage, >11GHz signal path bandwidth, 1mV input sensitivity, <2- ps rise/fall time, <16ps deterministic jitter, 1.5×1.5mm/sup 2/ die area and 30mA current from a 3.3V±10% supply voltage.