• DocumentCode
    2907537
  • Title

    Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions

  • Author

    Beyne, Eric

  • Author_Institution
    IMEC, Leuven, Belgium
  • fYear
    2012
  • fDate
    Jan. 31 2012-Feb. 2 2012
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    3D integration technology using thin die and Through-Silicon-Via, TSV, connections affect transistor and circuit behavior through electrical, mechanical and thermal interactions. The roadmap for further 3D technology development should focus on minimizing these effects.
  • Keywords
    CMOS integrated circuits; integrated circuit interconnections; three-dimensional integrated circuits; 3D TSV; 3D stacking technology; 3D technology development; CMOS devices; circuit behavior; electrical interaction; mechanical interaction; thermal interaction; through silicon vias; Silicon; Stacking; Stress; Temperature measurement; Thermal resistance; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2011 IEEE International
  • Conference_Location
    Osaka
  • Print_ISBN
    978-1-4673-2189-1
  • Type

    conf

  • DOI
    10.1109/3DIC.2012.6262977
  • Filename
    6262977
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2907537