An improved "soft" eFPGA design and implementation strategy

A recently proposed "soft" eFPGA methodology was used to create small amounts of programmable logic using the ASIC flow, but it incurs significant overhead. In this paper, it is shown that architecture-specific tactical standard cells can reduce the area and delay overhead of the previous approach by 58% and 40% respectively. It is also shown that by imposing a structured design and layout approach, the logic capacity and quality of standard-cell-based eFPGAs can be significantly improved. Finally, it is shown that our improved ASIC flow approach can create layouts that are competitive with another approach called GILES that uses custom FPGA CAD tools and nonstandard cells for tile layout purposes.