DocumentCode :
2907694
Title :
TSV reveal etch for 3D integration
Author :
Olson, Stephen ; Hummler, Klaus
Author_Institution :
SEMATECH, Albany, NY, USA
fYear :
2012
fDate :
Jan. 31 2012-Feb. 2 2012
Firstpage :
1
Lastpage :
4
Abstract :
In via-first and via-mid TSV integration flows, Si must be removed from the backside of the wafer to make contact with the bottom of the TSVs. This operation is performed using a mechanical grind followed by a reveal etch. We show the results of TSV reveal using both a wet and dry etch. A set of measurements is performed on the TSV wafers and the bonded stack to select etch parameters to achieve the desired TSV reveal height after the etch. We show that even extremely tight process control of the TSV etch, wafer grind, bond layer, carrier wafer thickness, and thinning etch will occasionally produce via heights that vary too much across the wafer and wafer to wafer. A CMP process is proposed that makes the thinning process simpler.
Keywords :
chemical mechanical polishing; etching; three-dimensional integrated circuits; wafer bonding; 3D integration; CMP process; TSV reveal etch; TSV reveal height; TSV wafers; bond layer; carrier wafer thickness; mechanical grind; thinning etch; via-first TSV integration flow; via-mid TSV integration flow; wafer grind; Bonding; Educational institutions; Process control; Silicon; Surface treatment; Thickness measurement; Through-silicon vias; 3D Integration; Through Silicon Via (TSV); Wafer thinning;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
3D Systems Integration Conference (3DIC), 2011 IEEE International
Conference_Location :
Osaka
Print_ISBN :
978-1-4673-2189-1
Type :
conf
DOI :
10.1109/3DIC.2012.6262987
Filename :
6262987
Link To Document :
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