Title :
Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor
Author :
Beacom, T. ; Buchholtz, T. ; Bradley, D. ; Randolph, J. ; Storino, S. ; Veldhuizen, M. ; Dance, S. ; Kuang, J.B. ; Schwinn, S. ; Cox, S. ; Ziegler, F. ; Kao, J. ; Li, C.T. ; Tretz, C. ; Cabellon, J. ; Freemyer, A. ; Tubbs, M.
Author_Institution :
Syst. & Technol. Group, IBM Rochester, NY, USA
Abstract :
This paper describes the design and implementation of the vector scalar unit (VSU) in the first-generation CELL processor. VSU executes floating-point and vector media extension instructions. VSU contains 1.7 million transistors and occupies an area of 3.1 mm2 in a 90nm PD-SOI technology. Extensive static and dynamic circuit techniques are used to optimize performance while minimizing area and power simultaneously. Full functionality is observed at 4.76 GHz, 1.3V supply and a chip temperature of 68°C.
Keywords :
integrated circuit design; logic design; low-power electronics; microprocessor chips; silicon-on-insulator; 1.3 V; 4.76 GHz; 68 C; 90 nm; PD-SOI technology; dual-thread vector scalar unit; first-generation CELL processor; floating point unit instructions; vector media extension instructions; Computer architecture; Energy management; Integrated circuit interconnections; Pipelines; Power control; Power dissipation; Signal design; Silicon on insulator technology; Temperature; Yarn;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568650
