The importance of including thermal effects in estimating the effectiveness of power reduction techniques

Author

Ku, Ja Chun ; Ghoneima, Maged ; Ismail, Yehea

Author_Institution

Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL

fYear

2005

fDate

21-21 Sept. 2005

Firstpage

301

Lastpage

304

Abstract

It is shown in this paper that thermal effects have to be an integral part of estimating the effectiveness of power reduction techniques in nanometer scale technologies, and its inclusion always results in higher reduction in power than conventional estimations. Four different power reduction techniques for on-chip buses are used as examples to show the necessity of including thermal effects. Simulation results in a 70nm technology show that thermal-aware estimations of power savings are 17-38% higher than conventional estimations that do not include thermal effects

Keywords

low-power electronics; nanoelectronics; system-on-chip; thermal analysis; 70 nm; higher reduction; nanometer scale technology; on-chip buses; power reduction technique; power savings; thermal effects; thermal-aware estimation; Delay; Design methodology; Design optimization; Electromigration; Energy consumption; Integrated circuit technology; Subthreshold current; Temperature dependence; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Conference_Location

San Jose, CA

Print_ISBN

0-7803-9023-7

Type

conf

DOI

10.1109/CICC.2005.1568665

Filename

1568665