Systematic design of digital algorithms for synchronization: from theory to VLSI

A methodology for the design and implementation of digital synchronization algorithms is discussed. Estimation theory is employed in the first step to systematically derive structures. Next, the performance of design alternatives is evaluated taking quantization and discretization into account. In the third step the algorithms are mapped onto a suitable processor architecture. The necessity for integrated simulation tools ranging from system level to the VLSI/DSP (digital signal processor) level in this highly interactive design process is emphasized. A design example involving DIRECS (Digital-Receiver Chip Set) is presented