DocumentCode
2908208
Title
Three Dimensional (3D) n-gate MOSFET
Author
Theng, A.L. ; Goh, W.L. ; Chan, Y.T. ; Tee, K.M. ; Chan, L. ; Ng, C.M.
Author_Institution
Nanyang Technol. Univ., Singapore
fYear
2007
fDate
26-28 Sept. 2007
Firstpage
33
Lastpage
36
Abstract
The concept of a three-dimensional (3D) n-gate MOSFET device SOI substrate has been proposed and developed in this work. This device consists of a rounded surface channel with gate extensions into the buried oxide for improved subthreshold behavior. The fabrication steps are compatible with the bulk CMOS process and it requires a mere addition of a reactive ion etching (RIE) etch step. Hence, the proposed n-gate transistor can be a viable replacement for bulk transistor in the near future.
Keywords
CMOS integrated circuits; MOSFET; silicon-on-insulator; 3D n-gate MOSFET; CMOS process; SOI substrate; buried oxide; n-gate transistor; reactive ion etching; CMOS process; Electrodes; Etching; Fabrication; MOSFET circuits; Oxidation; Rapid thermal processing; Semiconductor device manufacture; Shape; Silicon; MOS Devices; silicon-on-insulator(SOI);
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits, 2007. ISIC '07. International Symposium on
Conference_Location
Singapore
Print_ISBN
978-1-4244-0797-2
Electronic_ISBN
978-1-4244-0797-2
Type
conf
DOI
10.1109/ISICIR.2007.4441789
Filename
4441789
Link To Document