Title :
Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations
Author :
Qi, Xiaoning ; Lo, Sam C. ; Luo, Yansheng ; Gyure, Alex ; Shahram, Mahmoud ; Singhal, Kishore
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (∼9% push-out vs. RC delay) and noise (∼2× RC noise). Device and interconnect variations add ∼4% into RLC max-timing impact, while their impact on RLC signal noise is nonappreciable.
Keywords :
RLC circuits; VLSI; inductance; integrated circuit interconnections; nanoelectronics; system-on-chip; 90 nm; RC delay; RLC max-timing impact; RLC signal noise; VLSI interconnects; inductive impact; interconnect variations; on-chip buses; on-chip inductance impact; signal integrity; Analytical models; Delay; Inductance; Integrated circuit interconnections; Integrated circuit noise; PSNR; Signal design; Signal processing; Very large scale integration; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568667
