Low-power prediction based data transfer architecture

The energy dissipation of on-chip buses is becoming one of the main bottlenecks in current integrated circuits. This paper proposes a prediction-based technique to reduce data bus power dissipation. This technique uses value prediction to speculate the next value to transfer over the data bus. Two identical predictors are placed on the two ends of the bus. If the sender predictor accurately predicts the data to be transferred, data is not transmitted, and the bus energy dissipation is reduced. After implementing the proposed architecture in a 70nm CMOS technology, and using a representative subset of SPEC2K benchmarks, an average of 41% of the bus transitions were eliminated, which led to a 31% average overall energy reduction