Title :
A 500MHz DLL with second order duty cycle corrector for low jitter
Author :
Kim, Byung-Guk ; Oh, Kwang-Il ; Kim, Lee-Sup ; Lee, Dae-Woo
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., KAIST, Daejeon
Abstract :
A DLL with a second order duty cycle corrector which consists of a low pass filter and an integrator is presented. This paper shows the analysis and the design of the second order DCC for loop stability and low jitter. The DLL implemented in a 0.13mum CMOS process achieves an output duty error below plusmn1.6% within plusmn25% external input duty error. It has a 29.2 ps peak-to-peak jitter and a 3.8 ps RMS jitter
Keywords :
CMOS analogue integrated circuits; UHF circuits; circuit stability; delay lock loops; integrating circuits; low-pass filters; timing jitter; 0.13 micron; 29.2 ps; 3.8 ps; 500 MHz; CMOS process; DLL circuit; RMS jitter; external input duty error; integrating circuit; loop stability; low jitter; low pass filter; output duty error; peak-to-peak jitter; second order DCC; second order duty cycle corrector; Charge pumps; Circuit stability; Clocks; Degradation; Delay lines; Detectors; Integrated circuit modeling; Jitter; Laboratories; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-9023-7
DOI :
10.1109/CICC.2005.1568671
