Title :
On the fault location in combinational logic circuits
Author :
Rajsuman, R. ; Saad, M. ; Gupta, B.
Author_Institution :
Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Abstract :
A method is presented to identify and locate a fault in combinational logic circuits. A test pattern generator (called SPARK) has been developed, based on a modified version of the D-algorithm. A fault dictionary is set up during test generation. Through simulation, all activated lines under a test vector are identified. The test response is evaluated to identify possible paths which may have the fault. One does not stop testing as soon as a fault is detected. Based on circuit topology, the circuit is further exercised using fan-in and fan-out points to identify a faulty line segment or a gate. The fault location algorithm and experimental results on some combinational circuits are given
Keywords :
automatic testing; combinatorial circuits; fault location; logic CAD; logic testing; CAD; D-algorithm; SPARK; VLSI; circuit topology; combinational logic circuits; fan-in; fan-out; fault dictionary; fault location; simulation; test pattern generator; test response; test vector; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Dictionaries; Electrical fault detection; Fault diagnosis; Fault location; Sparks; Test pattern generators;
Conference_Titel :
Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on
Conference_Location :
Pacific Grove, CA
Print_ISBN :
0-8186-2470-1
DOI :
10.1109/ACSSC.1991.186647
