Memory-efficient logic layer communication platform for 3D-stacked memory-on-processor architectures

Three Dimensional (3D) chip stacking technology is emerging as a viable candidate to address the memory bandwidth problem by stacking multiple DRAM layers on top of a multiprocessor layer (logic layer) to reduce wire delay and energy consumption between them. In addition, combining the benefits of 3D memory-on-processor stacking architecture and on-chip networks provides a significant performance gain. To fully exploit the benefits of the 3D stacked memory-on-processor architectures, an efficient on-chip communication platform is required to be integrated in the logic layer. In this paper, we present an on-chip communication platform for the logic layer to exploit the potential bandwidth of stacked memory-on-processor architectures. This platform guarantees low-latency access to the stacked DRAM layers by employing an adaptive memory controller. Experimental results demonstrate that the proposed platform mitigates the average memory access latency (34%) and average memory utilization (31%) considerably and the overall performance gain is about 20%.